Only in ./auxprogs: CVS
Binary files ./auxprogs/genoffsets and /scratch/pgbovine/valgrind-3/vex/auxprogs/genoffsets differ
Only in /scratch/pgbovine/valgrind-3/vex/auxprogs: .svn
Only in .: CVS
Only in .: diff.txt
Only in ./docs: CVS
Only in ./docs: README
Only in /scratch/pgbovine/valgrind-3/vex/docs: .svn
Binary files ./libvex.a and /scratch/pgbovine/valgrind-3/vex/libvex.a differ
Only in /scratch/pgbovine/valgrind-3/vex/: nanoarm.orig
Only in ./orig_amd64: CVS
Only in /scratch/pgbovine/valgrind-3/vex/orig_amd64: .svn
Only in /scratch/pgbovine/valgrind-3/vex/orig_amd64: test1.orig
Only in /scratch/pgbovine/valgrind-3/vex/orig_amd64: test2.orig
Only in ./orig_arm: CVS
Only in /scratch/pgbovine/valgrind-3/vex/orig_arm: nanoarm.orig
Only in /scratch/pgbovine/valgrind-3/vex/orig_arm: .svn
Only in /scratch/pgbovine/valgrind-3/vex/: orig_ppc32
Only in /scratch/pgbovine/valgrind-3/vex/: orig_x86
Only in ./priv: CVS
Only in ./priv/guest-amd64: CVS
Binary files ./priv/guest-amd64/ghelpers.o and /scratch/pgbovine/valgrind-3/vex/priv/guest-amd64/ghelpers.o differ
Only in /scratch/pgbovine/valgrind-3/vex/priv/guest-amd64: .svn
Binary files ./priv/guest-amd64/toIR.o and /scratch/pgbovine/valgrind-3/vex/priv/guest-amd64/toIR.o differ
Only in ./priv/guest-arm: CVS
Binary files ./priv/guest-arm/ghelpers.o and /scratch/pgbovine/valgrind-3/vex/priv/guest-arm/ghelpers.o differ
Only in /scratch/pgbovine/valgrind-3/vex/priv/guest-arm: .svn
Binary files ./priv/guest-arm/toIR.o and /scratch/pgbovine/valgrind-3/vex/priv/guest-arm/toIR.o differ
Only in ./priv/guest-generic: CVS
Binary files ./priv/guest-generic/g_generic_x87.o and /scratch/pgbovine/valgrind-3/vex/priv/guest-generic/g_generic_x87.o differ
Only in /scratch/pgbovine/valgrind-3/vex/priv/guest-generic: .svn
Only in ./priv/guest-ppc32: CVS
Binary files ./priv/guest-ppc32/ghelpers.o and /scratch/pgbovine/valgrind-3/vex/priv/guest-ppc32/ghelpers.o differ
Only in /scratch/pgbovine/valgrind-3/vex/priv/guest-ppc32: .svn
Binary files ./priv/guest-ppc32/toIR.o and /scratch/pgbovine/valgrind-3/vex/priv/guest-ppc32/toIR.o differ
Only in ./priv/guest-x86: CVS
Binary files ./priv/guest-x86/ghelpers.o and /scratch/pgbovine/valgrind-3/vex/priv/guest-x86/ghelpers.o differ
Only in /scratch/pgbovine/valgrind-3/vex/priv/guest-x86: .svn
Binary files ./priv/guest-x86/toIR.o and /scratch/pgbovine/valgrind-3/vex/priv/guest-x86/toIR.o differ
Only in ./priv/host-amd64: CVS
Binary files ./priv/host-amd64/hdefs.o and /scratch/pgbovine/valgrind-3/vex/priv/host-amd64/hdefs.o differ
diff -urb ./priv/host-amd64/isel.c /scratch/pgbovine/valgrind-3/vex/priv/host-amd64/isel.c
--- ./priv/host-amd64/isel.c	2005-04-11 15:56:46.000000000 -0400
+++ /scratch/pgbovine/valgrind-3/vex/priv/host-amd64/isel.c	2005-04-25 16:45:09.000000000 -0400
@@ -87,11 +87,11 @@
 //.. {
 //..    return IRExpr_Const(IRConst_U64(i));
 //.. }
-//.. 
-//.. static IRExpr* mkU32 ( UInt i )
-//.. {
-//..    return IRExpr_Const(IRConst_U32(i));
-//.. }
+
+static IRExpr* mkU32 ( UInt i )
+{
+   return IRExpr_Const(IRConst_U32(i));
+}
 
 static IRExpr* bind ( Int binder )
 {
@@ -991,31 +991,20 @@
          return hi16;
       }
 
-//..       if (e->Iex.Binop.op == Iop_8HLto16) {
-//..          HReg hi8  = newVRegI(env);
-//..          HReg lo8  = newVRegI(env);
-//..          HReg hi8s = iselIntExpr_R(env, e->Iex.Binop.arg1);
-//..          HReg lo8s = iselIntExpr_R(env, e->Iex.Binop.arg2);
-//..          addInstr(env, mk_iMOVsd_RR(hi8s, hi8));
-//..          addInstr(env, mk_iMOVsd_RR(lo8s, lo8));
-//..          addInstr(env, X86Instr_Sh32(Xsh_SHL, 8, X86RM_Reg(hi8)));
-//..          addInstr(env, X86Instr_Alu32R(Xalu_AND, X86RMI_Imm(0xFF), lo8));
-//..          addInstr(env, X86Instr_Alu32R(Xalu_OR, X86RMI_Reg(lo8), hi8));
-//..          return hi8;
-//..       }
-//.. 
-//..       if (e->Iex.Binop.op == Iop_16HLto32) {
-//..          HReg hi16  = newVRegI(env);
-//..          HReg lo16  = newVRegI(env);
-//..          HReg hi16s = iselIntExpr_R(env, e->Iex.Binop.arg1);
-//..          HReg lo16s = iselIntExpr_R(env, e->Iex.Binop.arg2);
-//..          addInstr(env, mk_iMOVsd_RR(hi16s, hi16));
-//..          addInstr(env, mk_iMOVsd_RR(lo16s, lo16));
-//..          addInstr(env, X86Instr_Sh32(Xsh_SHL, 16, X86RM_Reg(hi16)));
-//..          addInstr(env, X86Instr_Alu32R(Xalu_AND, X86RMI_Imm(0xFFFF), lo16));
-//..          addInstr(env, X86Instr_Alu32R(Xalu_OR, X86RMI_Reg(lo16), hi16));
-//..          return hi16;
-//..       }
+      if (e->Iex.Binop.op == Iop_8HLto16) {
+         HReg hi8  = newVRegI(env);
+         HReg lo8  = newVRegI(env);
+         HReg hi8s = iselIntExpr_R(env, e->Iex.Binop.arg1);
+         HReg lo8s = iselIntExpr_R(env, e->Iex.Binop.arg2);
+         addInstr(env, mk_iMOVsd_RR(hi8s, hi8));
+         addInstr(env, mk_iMOVsd_RR(lo8s, lo8));
+         addInstr(env, AMD64Instr_Sh64(Ash_SHL, 8, AMD64RM_Reg(hi8)));
+         addInstr(env, AMD64Instr_Alu64R(
+                          Aalu_AND, AMD64RMI_Imm(0xFF), lo8));
+         addInstr(env, AMD64Instr_Alu64R(
+                          Aalu_OR, AMD64RMI_Reg(lo8), hi8));
+         return hi8;
+      }
 
       if (e->Iex.Binop.op == Iop_MullS32
           || e->Iex.Binop.op == Iop_MullS16
@@ -1282,17 +1271,18 @@
             addInstr(env, AMD64Instr_Set64(cond,dst));
             return dst;
          }
-//..          case Iop_1Sto8:
-//..          case Iop_1Sto16:
-//..          case Iop_1Sto32: {
-//..             /* could do better than this, but for now ... */
-//..             HReg dst         = newVRegI(env);
-//..             X86CondCode cond = iselCondCode(env, e->Iex.Unop.arg);
-//..             addInstr(env, X86Instr_Set32(cond,dst));
-//..             addInstr(env, X86Instr_Sh32(Xsh_SHL, 31, X86RM_Reg(dst)));
-//..             addInstr(env, X86Instr_Sh32(Xsh_SAR, 31, X86RM_Reg(dst)));
-//..             return dst;
-//..          }
+         case Iop_1Sto8:
+         case Iop_1Sto16:
+         case Iop_1Sto32:
+         case Iop_1Sto64: {
+            /* could do better than this, but for now ... */
+            HReg dst           = newVRegI(env);
+            AMD64CondCode cond = iselCondCode(env, e->Iex.Unop.arg);
+            addInstr(env, AMD64Instr_Set64(cond,dst));
+            addInstr(env, AMD64Instr_Sh64(Ash_SHL, 63, AMD64RM_Reg(dst)));
+            addInstr(env, AMD64Instr_Sh64(Ash_SAR, 63, AMD64RM_Reg(dst)));
+            return dst;
+         }
          case Iop_Ctz64: {
             /* Count trailing zeroes, implemented by amd64 'bsfq' */
             HReg dst = newVRegI(env);
@@ -1315,17 +1305,14 @@
             return dst;
          }
 
-//..          case Iop_128to32: {
-//..             HReg      dst  = newVRegI(env);
-//..             HReg      vec  = iselVecExpr(env, e->Iex.Unop.arg);
-//..             X86AMode* esp0 = X86AMode_IR(0, hregX86_ESP());
-//..             sub_from_esp(env, 16);
-//..             addInstr(env, X86Instr_SseLdSt(False/*store*/, vec, esp0));
-//..             addInstr(env, X86Instr_Alu32R( Xalu_MOV, X86RMI_Mem(esp0), dst ));
-//..             add_to_esp(env, 16);
-//..             return dst;
-//..          }
-
+         case Iop_V128to32: {
+            HReg        dst     = newVRegI(env);
+            HReg        vec     = iselVecExpr(env, e->Iex.Unop.arg);
+            AMD64AMode* rsp_m16 = AMD64AMode_IR(-16, hregAMD64_RSP());
+            addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, vec, rsp_m16));
+            addInstr(env, AMD64Instr_LoadEX(4, False/*z-widen*/, rsp_m16, dst));
+            return dst;
+         }
 
          /* V128{HI}to64 */
          case Iop_V128HIto64:
@@ -1405,6 +1392,10 @@
          addInstr(env, AMD64Instr_LoadEX( 1, False, am, dst ));
          return dst;
       }
+      if (ty == Ity_I64) {
+         addInstr(env, AMD64Instr_Alu64R( Aalu_MOV, AMD64RMI_Mem(am), dst ));
+         return dst;
+      }
       break;
    }
 
@@ -1798,23 +1789,41 @@
       return Acc_NZ;
    }
 
-//..    /* CmpEQ8 / CmpNE8 */
-//..    if (e->tag == Iex_Binop 
-//..        && (e->Iex.Binop.op == Iop_CmpEQ8
-//..            || e->Iex.Binop.op == Iop_CmpNE8)) {
-//..       HReg    r1   = iselIntExpr_R(env, e->Iex.Binop.arg1);
-//..       X86RMI* rmi2 = iselIntExpr_RMI(env, e->Iex.Binop.arg2);
-//..       HReg    r    = newVRegI(env);
-//..       addInstr(env, mk_iMOVsd_RR(r1,r));
-//..       addInstr(env, X86Instr_Alu32R(Xalu_XOR,rmi2,r));
-//..       addInstr(env, X86Instr_Alu32R(Xalu_AND,X86RMI_Imm(0xFF),r));
-//..       switch (e->Iex.Binop.op) {
-//..          case Iop_CmpEQ8:  return Xcc_Z;
-//..          case Iop_CmpNE8:  return Xcc_NZ;
-//..          default: vpanic("iselCondCode(x86): CmpXX8");
-//..       }
-//..    }
-//.. 
+   /* CmpEQ8 / CmpNE8 */
+   if (e->tag == Iex_Binop 
+       && (e->Iex.Binop.op == Iop_CmpEQ8
+           || e->Iex.Binop.op == Iop_CmpNE8)) {
+      HReg      r1   = iselIntExpr_R(env, e->Iex.Binop.arg1);
+      AMD64RMI* rmi2 = iselIntExpr_RMI(env, e->Iex.Binop.arg2);
+      HReg      r    = newVRegI(env);
+      addInstr(env, mk_iMOVsd_RR(r1,r));
+      addInstr(env, AMD64Instr_Alu64R(Aalu_XOR,rmi2,r));
+      addInstr(env, AMD64Instr_Alu64R(Aalu_AND,AMD64RMI_Imm(0xFF),r));
+      switch (e->Iex.Binop.op) {
+         case Iop_CmpEQ8:  return Acc_Z;
+         case Iop_CmpNE8:  return Acc_NZ;
+         default: vpanic("iselCondCode(amd64): CmpXX8");
+      }
+   }
+
+   /* CmpEQ32 / CmpNE32 */
+   if (e->tag == Iex_Binop 
+       && (e->Iex.Binop.op == Iop_CmpEQ32
+           || e->Iex.Binop.op == Iop_CmpNE32)) {
+      HReg      r1   = iselIntExpr_R(env, e->Iex.Binop.arg1);
+      AMD64RMI* rmi2 = iselIntExpr_RMI(env, e->Iex.Binop.arg2);
+      HReg      r    = newVRegI(env);
+      addInstr(env, mk_iMOVsd_RR(r1,r));
+      addInstr(env, AMD64Instr_Alu64R(Aalu_XOR,rmi2,r));
+      addInstr(env, AMD64Instr_Sh64(Ash_SHL, 32, AMD64RM_Reg(r)));
+      switch (e->Iex.Binop.op) {
+         case Iop_CmpEQ32:  return Acc_Z;
+         case Iop_CmpNE32:  return Acc_NZ;
+         default: vpanic("iselCondCode(amd64): CmpXX8");
+      }
+   }
+
+
 //..    /* CmpEQ16 / CmpNE16 */
 //..    if (e->tag == Iex_Binop 
 //..        && (e->Iex.Binop.op == Iop_CmpEQ16
@@ -1831,17 +1840,17 @@
 //..          default: vpanic("iselCondCode(x86): CmpXX16");
 //..       }
 //..    }
-//.. 
-//..    /* CmpNE32(1Sto32(b), 0) ==> b */
-//..    {
-//..       DECLARE_PATTERN(p_CmpNE32_1Sto32);
-//..       DEFINE_PATTERN(
-//..          p_CmpNE32_1Sto32,
-//..          binop(Iop_CmpNE32, unop(Iop_1Sto32,bind(0)), mkU32(0)));
-//..       if (matchIRExpr(&mi, p_CmpNE32_1Sto32, e)) {
-//..          return iselCondCode(env, mi.bindee[0]);
-//..       }
-//..    }
+
+   /* CmpNE32(1Sto32(b), 0) ==> b */
+   {
+      DECLARE_PATTERN(p_CmpNE32_1Sto32);
+      DEFINE_PATTERN(
+         p_CmpNE32_1Sto32,
+         binop(Iop_CmpNE32, unop(Iop_1Sto32,bind(0)), mkU32(0)));
+      if (matchIRExpr(&mi, p_CmpNE32_1Sto32, e)) {
+         return iselCondCode(env, mi.bindee[0]);
+      }
+   }
 
    /* Cmp*64*(x,y) */
    if (e->tag == Iex_Binop 
@@ -3171,29 +3180,25 @@
    if (e->tag == Iex_Binop) {
    switch (e->Iex.Binop.op) {
 
-//..       case Iop_Set128lo32: {
-//..          HReg dst = newVRegV(env);
-//..          HReg srcV = iselVecExpr(env, e->Iex.Binop.arg1);
-//..          HReg srcI = iselIntExpr_R(env, e->Iex.Binop.arg2);
-//..          X86AMode* esp0 = X86AMode_IR(0, hregX86_ESP());
-//..          sub_from_esp(env, 16);
-//..          addInstr(env, X86Instr_SseLdSt(False/*store*/, srcV, esp0));
-//..          addInstr(env, X86Instr_Alu32M(Xalu_MOV, X86RI_Reg(srcI), esp0));
-//..          addInstr(env, X86Instr_SseLdSt(True/*load*/, dst, esp0));
-//..          add_to_esp(env, 16);
-//..          return dst;
-//..       }
-
       case Iop_SetV128lo64: {
          HReg dst  = newVRegV(env);
          HReg srcV = iselVecExpr(env, e->Iex.Binop.arg1);
          HReg srcI = iselIntExpr_R(env, e->Iex.Binop.arg2);
-         AMD64AMode* rsp0 = AMD64AMode_IR(0, hregAMD64_RSP());
-         sub_from_rsp(env, 16);
-         addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, srcV, rsp0));
-         addInstr(env, AMD64Instr_Alu64M(Aalu_MOV, AMD64RI_Reg(srcI), rsp0));
-         addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, dst, rsp0));
-         add_to_rsp(env, 16);
+         AMD64AMode* rsp_m16 = AMD64AMode_IR(-16, hregAMD64_RSP());
+         addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, srcV, rsp_m16));
+         addInstr(env, AMD64Instr_Alu64M(Aalu_MOV, AMD64RI_Reg(srcI), rsp_m16));
+         addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, dst, rsp_m16));
+         return dst;
+      }
+
+      case Iop_SetV128lo32: {
+         HReg dst  = newVRegV(env);
+         HReg srcV = iselVecExpr(env, e->Iex.Binop.arg1);
+         HReg srcI = iselIntExpr_R(env, e->Iex.Binop.arg2);
+         AMD64AMode* rsp_m16 = AMD64AMode_IR(-16, hregAMD64_RSP());
+         addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, srcV, rsp_m16));
+         addInstr(env, AMD64Instr_Store(4, srcI, rsp_m16));
+         addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, dst, rsp_m16));
          return dst;
       }
 
@@ -3535,14 +3540,11 @@
          addInstr(env, AMD64Instr_Store( 1, r, am ));
          return;
       }
-//..       if (ty == Ity_I64) {
-//..          HReg rHi, rLo;
-//..          X86AMode* am4 = advance4(am);
-//..          iselInt64Expr(&rHi, &rLo, env, stmt->Ist.PutI.data);
-//..          addInstr(env, X86Instr_Alu32M( Xalu_MOV, X86RI_Reg(rLo), am ));
-//..          addInstr(env, X86Instr_Alu32M( Xalu_MOV, X86RI_Reg(rHi), am4 ));
-//..          return;
-//..       }
+      if (ty == Ity_I64) {
+         AMD64RI* ri = iselIntExpr_RI(env, stmt->Ist.PutI.data);
+         addInstr(env, AMD64Instr_Alu64M( Aalu_MOV, ri, am ));
+         return;
+      }
       break;
    }
 
@@ -3612,7 +3614,8 @@
          return;
 
       retty = typeOfIRTemp(env->type_env, d->tmp);
-      if (retty == Ity_I64) {
+      if (retty == Ity_I64 || retty == Ity_I32 
+          || retty == Ity_I16 || retty == Ity_I8) {
          /* The returned value is in %rax.  Park it in the register
             associated with tmp. */
          HReg dst = lookupIRTemp(env, d->tmp);
Binary files ./priv/host-amd64/isel.o and /scratch/pgbovine/valgrind-3/vex/priv/host-amd64/isel.o differ
Only in /scratch/pgbovine/valgrind-3/vex/priv/host-amd64: .svn
Only in ./priv/host-arm: CVS
Binary files ./priv/host-arm/hdefs.o and /scratch/pgbovine/valgrind-3/vex/priv/host-arm/hdefs.o differ
Binary files ./priv/host-arm/isel.o and /scratch/pgbovine/valgrind-3/vex/priv/host-arm/isel.o differ
Only in /scratch/pgbovine/valgrind-3/vex/priv/host-arm: .svn
Only in ./priv/host-generic: CVS
Binary files ./priv/host-generic/h_generic_regs.o and /scratch/pgbovine/valgrind-3/vex/priv/host-generic/h_generic_regs.o differ
Binary files ./priv/host-generic/h_generic_simd64.o and /scratch/pgbovine/valgrind-3/vex/priv/host-generic/h_generic_simd64.o differ
Only in ./priv/host-generic: reg_alloc2.c~
Binary files ./priv/host-generic/reg_alloc2.o and /scratch/pgbovine/valgrind-3/vex/priv/host-generic/reg_alloc2.o differ
Only in /scratch/pgbovine/valgrind-3/vex/priv/host-generic: .svn
Only in ./priv/host-ppc32: CVS
Binary files ./priv/host-ppc32/hdefs.o and /scratch/pgbovine/valgrind-3/vex/priv/host-ppc32/hdefs.o differ
Binary files ./priv/host-ppc32/isel.o and /scratch/pgbovine/valgrind-3/vex/priv/host-ppc32/isel.o differ
Only in /scratch/pgbovine/valgrind-3/vex/priv/host-ppc32: .svn
Only in ./priv/host-x86: CVS
Binary files ./priv/host-x86/hdefs.o and /scratch/pgbovine/valgrind-3/vex/priv/host-x86/hdefs.o differ
diff -urb ./priv/host-x86/isel.c /scratch/pgbovine/valgrind-3/vex/priv/host-x86/isel.c
--- ./priv/host-x86/isel.c	2005-04-25 16:24:03.000000000 -0400
+++ /scratch/pgbovine/valgrind-3/vex/priv/host-x86/isel.c	2005-04-25 16:45:08.000000000 -0400
@@ -44,9 +44,11 @@
 #include "host-generic/h_generic_simd64.h"
 #include "host-x86/hdefs.h"
 
-/* TODO 4 Feb 2005:
+/* TODO 21 Apr 2005:
 
-   -- Fill in load-case in iselIntExpr_RMI
+   -- (Really an assembler issue) don't emit CMov32 as a cmov
+      insn, since that's expensive on P4 and conditional branch
+      is cheaper if (as we expect) the condition is highly predictable
 
    -- preserve xmm registers across function calls (by declaring them
       as trashed by call insns)
Only in ./priv/host-x86: isel.c~
Only in ./priv/host-x86: .#isel.c.1.1.1.1
Binary files ./priv/host-x86/isel.o and /scratch/pgbovine/valgrind-3/vex/priv/host-x86/isel.o differ
Only in /scratch/pgbovine/valgrind-3/vex/priv/host-x86: .svn
Only in ./priv/ir: CVS
Binary files ./priv/ir/irdefs.o and /scratch/pgbovine/valgrind-3/vex/priv/ir/irdefs.o differ
Binary files ./priv/ir/irmatch.o and /scratch/pgbovine/valgrind-3/vex/priv/ir/irmatch.o differ
diff -urb ./priv/ir/iropt.c /scratch/pgbovine/valgrind-3/vex/priv/ir/iropt.c
--- ./priv/ir/iropt.c	2005-04-11 15:56:46.000000000 -0400
+++ /scratch/pgbovine/valgrind-3/vex/priv/ir/iropt.c	2005-04-25 16:45:10.000000000 -0400
@@ -1228,6 +1228,13 @@
             e2 = e->Iex.Binop.arg1;
          } else
 
+         /* Or8(x,0) ==> x */
+         if ((e->Iex.Binop.op == Iop_Or8)
+             && e->Iex.Binop.arg2->tag == Iex_Const
+             && e->Iex.Binop.arg2->Iex.Const.con->Ico.U8 == 0) {
+            e2 = e->Iex.Binop.arg1;
+         } else
+
          /* Or32/Add32(x,0) ==> x */
          if ((e->Iex.Binop.op == Iop_Add32 || e->Iex.Binop.op == Iop_Or32)
              && e->Iex.Binop.arg2->tag == Iex_Const
Binary files ./priv/ir/iropt.o and /scratch/pgbovine/valgrind-3/vex/priv/ir/iropt.o differ
Only in /scratch/pgbovine/valgrind-3/vex/priv/ir: .svn
Only in ./priv/main: CVS
Only in /scratch/pgbovine/valgrind-3/vex/priv/main: .svn
Binary files ./priv/main/vex_globals.o and /scratch/pgbovine/valgrind-3/vex/priv/main/vex_globals.o differ
Binary files ./priv/main/vex_main.o and /scratch/pgbovine/valgrind-3/vex/priv/main/vex_main.o differ
diff -urb ./priv/main/vex_svnversion.h /scratch/pgbovine/valgrind-3/vex/priv/main/vex_svnversion.h
--- ./priv/main/vex_svnversion.h	2005-04-11 16:54:29.000000000 -0400
+++ /scratch/pgbovine/valgrind-3/vex/priv/main/vex_svnversion.h	2005-04-25 16:45:48.000000000 -0400
@@ -1 +1 @@
-"1130"
+"1139"
Binary files ./priv/main/vex_util.o and /scratch/pgbovine/valgrind-3/vex/priv/main/vex_util.o differ
Only in /scratch/pgbovine/valgrind-3/vex/priv: .svn
Only in ./pub: CVS
diff -urb ./pub/libvex_ir.h /scratch/pgbovine/valgrind-3/vex/pub/libvex_ir.h
--- ./pub/libvex_ir.h	2005-04-11 15:56:48.000000000 -0400
+++ /scratch/pgbovine/valgrind-3/vex/pub/libvex_ir.h	2005-04-25 16:45:11.000000000 -0400
@@ -383,7 +383,7 @@
       Iop_MulHi16Ux4,
       Iop_MulHi16Sx4,
 
-      /* AVERAGING: note: (arg1 + arg2 + 1) >> 1 */
+      /* AVERAGING: note: (arg1 + arg2 + 1) >>u 1 */
       Iop_Avg8Ux8,
       Iop_Avg16Ux4,
 
@@ -500,7 +500,7 @@
       Iop_MulHi16Ux8,
       Iop_MulHi16Sx8,
 
-      /* AVERAGING: note: (arg1 + arg2 + 1) >> 1 */
+      /* AVERAGING: note: (arg1 + arg2 + 1) >>u 1 */
       Iop_Avg8Ux16,
       Iop_Avg16Ux8,
 
@@ -562,21 +562,36 @@
 
    IRExpr_GetI (also IRStmt_PutI)
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-   This carries two ints, which give the lowest and highest possible
-   byte offsets that the GetI can possibly reference.  For example, if
-   the type is Ity_I32, and the Expr may have a value of M, M+4 or
-   M+8, where M is a translation-time known constant, then the low and
-   high limits are M and M+11 respectively.
+   These allow circular indexing into parts of the guest state, which
+   is essential for modelling situations where the identity of guest
+   registers is not known until run time.  One example is the x87 FP
+   register stack.
 
-   PutI's limit values are interpreted identically.
+   The part of the guest state to be treated as a circular array is
+   described in an IRArray structure attached to the GetI/PutI.
+   IRArray holds the offset of the first element in the array, the
+   type of each element, and the number of elements.
 
-   The limit values are used by IR optimisers to establish
+   The array index is indicated rather indirectly, in a way which
+   makes optimisation easy: as the sum of variable part (the 'ix'
+   field) and a constant offset (the 'bias' field).
+
+   Since the indexing is circular, the actual array index to use
+   is computed as (ix + bias) % number-of-elements-in-the-array.
+
+   Here's an example.  The description
+
+      (96:8xF64)[t39,-7]
+
+   describes an array of 8 F64-typed values, the guest-state-offset
+   of the first being 96.  This array is being indexed at
+   (t39 - 7) % 8.
+
+   It is important to get the array size/type exactly correct since IR
+   optimisation looks closely at such info in order to establish
    aliasing/non-aliasing between seperate GetI and PutI events, which
-   could be used to do reordering of them, or suchlike things.
-   Clearly it's critical to give the correct limit values -- this is
-   something that can't be automatically checked (in general), and so
-   the front-end writers must be very careful to tell the truth, since
-   not doing so could lead to obscure IR optimisation bugs.
+   is used to establish when they can be reordered, etc.  Putting
+   incorrect info in will lead to obscure IR optimisation bugs.
 
    IRExpr_CCall
    ~~~~~~~~~~~~
@@ -609,8 +624,7 @@
    details about what the helper does (and you better be telling the
    truth, otherwise any derived instrumentation will be wrong).  Also
    IRStmt_Dirty inhibits various IR optimisations and so can cause
-   quite poor code to be generated.  Try to avoid it.  
-*/
+   quite poor code to be generated.  Try to avoid it.  */
 
 /* The possible kinds of expressions are as follows: */
 typedef
Only in /scratch/pgbovine/valgrind-3/vex/pub: .svn
Only in /scratch/pgbovine/valgrind-3/vex/: .svn
Only in ./switchback: CVS
Only in /scratch/pgbovine/valgrind-3/vex/switchback: .svn
Only in ./test: CVS
Only in /scratch/pgbovine/valgrind-3/vex/test: .svn
Binary files ./test_main.o and /scratch/pgbovine/valgrind-3/vex/test_main.o differ
diff -urb ./TODO.txt /scratch/pgbovine/valgrind-3/vex/TODO.txt
--- ./TODO.txt	2005-04-11 15:56:45.000000000 -0400
+++ /scratch/pgbovine/valgrind-3/vex/TODO.txt	2005-04-25 16:45:19.000000000 -0400
@@ -12,21 +12,12 @@
 x86 guest: look at FP accuracy
 
 
-Test
-~~~~
-Test adc/sbb carry dependency in memcheck
-
-
 Optimisation opportunities
 ~~~~~~~~~~~~~~~~~~~~~~~~~~
 Improved isel for memcheck artefacts on x86 (generate neg ; sbbl)
 
 Assess tt_fast miss rates 
 
-Better register allocation - spilling reduction
-
-iropt less conservative re precise exns
-
 improve stack-update pass
 
 proper profiling machinery
@@ -35,6 +26,7 @@
 
 x86 iselIntExpr_RMI: actually generate the M case if possible
 
+
 JIT speedups
 ~~~~~~~~~~~~
 Ensure incremental flatness throughout
@@ -54,19 +46,10 @@
 
 disallow dirty helpers from writing SP/IP
 
-make instrumentation work at no optimisation
-
 write API doc, clarify IR semantics
 
 make IR utils module
 
-tt/tc simplification, also profiling
-
 generic stack pointer identification at startup?
 
 New memstack_k: old or new sp?
-
-Set host FPU mode before starting.  Also set Dflag = 0 
-
-skin_panic -> tool_panic
-
diff -urb ./unused/arena.h /scratch/pgbovine/valgrind-3/vex/unused/arena.h
--- ./unused/arena.h	2005-04-11 15:56:49.000000000 -0400
+++ /scratch/pgbovine/valgrind-3/vex/unused/arena.h	2005-04-25 16:45:12.000000000 -0400
@@ -22,10 +22,10 @@
 ITS FITNESS FOR ANY PARTICULAR PURPOSE.
 
 David Hanson / drh@microsoft.com / http://www.research.microsoft.com/~drh/
-$Id: arena.h,v 1.1.1.1 2005/04/11 19:56:49 pgbovine Exp $
+$Id: CPYRIGHT,v 1.2 1997/11/04 22:31:40 drh Exp $
 */
 
-/* $Id: arena.h,v 1.1.1.1 2005/04/11 19:56:49 pgbovine Exp $ */
+/* $Id: H:/drh/idioms/book/RCS/arena.doc,v 1.10 1997/02/21 19:45:19 drh Exp $ */
 
 #ifndef _CII_ARENA_H
 #define _CII_ARENA_H
Only in ./unused: CVS
Only in /scratch/pgbovine/valgrind-3/vex/unused: .svn
Only in ./useful: CVS
Only in /scratch/pgbovine/valgrind-3/vex/useful: .svn
Binary files ./vex and /scratch/pgbovine/valgrind-3/vex/vex differ
